1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a combined stacktrench.
2. Background and Related Art
As the demand and utility of memory devices escalates, it is increasingly important to develop large capacity memory devices. It also is equally important to minimize the semiconductor area required for such memory devices, thereby increasing the packing density. Considerable progress has been achieved in increasing the density of DRAM (Dynamic Random Access Memory) by producing an individual memory cell having a single capacitor and a single transistor. To further increase packing density, this memory cell has been converted from the traditional planar-type capacitor cell structure to three-dimensional stack-type and trench-type capacitor cell structures.
When manufacturing a trench-type capacitor, anisotropic etching is employed to produce thin trenches on the surface of the substrate. The resultant side walls of the trenches are utilized as the capacitor region, thereby providing large capacitance within a narrow region.
However, the conventional trench-type capacitor has several drawbacks which are likely to occur during scaling-down work including soft errors resulting from alpha particles and leakage current between the trenches.
On the other hand, a stack-type capacitor is manufactured by stacking a capacitor upon a silicon substrate. The stack-type capacitor is advantageous because soft errors are minimized due to a small diffusion region, and the manufacturing process is relatively simple. However, it is difficult to grow a dielectric film for stack-type capacitors. Further, the stack-type capacitor has a step coverage problem due to the stacked structure of the capacitor upon a transistor.
To employ three-dimensional capacitor cell structures in UVLSI memory devices on the order of sub-half-micron, a topologically high stack-type capacitor or a combined stack-trench type capacitor has been proposed. The conventional manufacturing process for the combined stack-trench type capacitor is illustrated in FIGS. 1A to 1D, and will be described below in detail.
As illustrated in FIG. 1A, an active region is defined by growing a field oxide layer 101 on a semiconductor substrate 100. A gate electrode 2, a source region 3 and a drain region 4 of a transistor, which is a part of the memory cell, are formed on the active region. A first conductive layer 5 (e.g., an impurity-doped polycrystalline silicon layer) is formed on the field oxide layer 101 such that it is connected with a gate electrode of a memory cell disposed adjacently to any predetermined portion of the field oxide layer 10;. An insulating layer 6 is then formed over the surface of the whole structure described above.
A trench 10 is etched between the field oxide layer 101 and the gate electrode 2 and through the insulating layer 6. The sharp corners of the trench 10 are then rounded off. A sacrificial oxide layer 11, having a thickness of 100.ANG.-1000.ANG., is formed on both the inside of the trench and on the insulating layer 6 to minimize any damage which might have occurred during the formation of the trench 10.
As illustrated in FIG. 1B, the sacrificial oxide layer 11 is removed, and a second conductive layer 12 (e.g., an impurity-doped polycrystalline silicon layer) is formed on both the inside of the trench 10 and the insulating layer 6. The second conductive layer 12 has a thickness of 500.ANG.-3000.ANG. and is used as a first electrode of the capacitor. A mask or photoresist technique is then performed upon the second conductive layer 12 to form a photoresist pattern 20.
In FIG. 1C, the second conductive layer 12 is etched according to the photoresist pattern 20 to form a first electrode pattern 12a. A dielectric film 13 is then formed to cover the surface of the first electrode pattern 12a.
As illustrated in FIG. 1D, a third conductive layer 14 (e.g., an impurity-doped polycrystalline silicon layer) is formed over the entire structure. The third conductive layer 14 is used as a second electrode of the capacitor, thereby completing the conventional combined stack-trench type capacitor.
However, the conventional manufacturing method described above has drawbacks which reduce the effectiveness of the capacitor cell. Since the first electrode pattern is formed via a photoetching process, by-products (principally, polymers with carbon atoms as the main element) produced during the photoetching process adhere on the side walls of the trench, thereby causing a non-uniform formation of the dielectric film. Further, when the capacitor is completed by depositing the third conductive layer on the non-uniform dielectric film, the electrical characteristics of the capacitor are aggravated, thereby impairing the reliability of the capacitor.